Power Integrity
As signal edge rates get faster, designers of today's high-speed digital pc boards encounter problems that were unimaginable a few years ago. Trial and error are time-consuming and expensive, often resulting in over-constrained designs that unnecessarily increase manufacturing costs. Sedona’s SMEs will analyze and optimize board design and board real estate usage to identify potential board configurations. Using a trial-and-error approach to optimize the power integrity of a pc board requires multiple design cycles and potentially higher cost compared with simulation of virtual prototypes.
Sedona can:
- Obtain impedance profiles of the power system network
- Perform analysis in the frequency domain (noise at various frequencies and resonant behaviour)
- Perform analysis in the time domain (noise at various points of time).
- Perform isolation studies
- Decoupling design involving:
- Capacitor placement and selection (dielectric types, body sizes and values),
- Via placement, capacitor landing pad design,
- Ferrite bead selection,
- And the design and analysis of power islands / power splits.
Sedona SMEs will reduce design cycles and deliver a cost effective design.