Signal Integrity

With shrinking process geometries and rising clock frequencies, it is essential for designers to address Signal Integrity (SI) problems to meet timing closure.

  • Stack up: Material / Analysis / Planning
  • Pre & post route signal simulations
  • Rules documentation & creation
  • Timing Analysis
  • Clock skew, clock distribution, reflections and crosstalk analysis
  • ASIC I/O Pin-out and cell selection
  • IBIS model creation
  • HSPICE to IBIS model conversion and verification
  • 3D S-Parameter modeling
  • Power integrity, EMI/EMC, analysis
  • SME Design review service

Industry recognized Subject Matter Expert (SME)Specctraquest, Hyperlinx, Integrated PCB/SI Processes

SI Analysis

  • Develop and understand system environment
  • Developing critical signal quality checks
  • Identify critical timing requirements
  • Build libraries (IO buffers, Interconnect, Package, Connectors)
  • 2D/3D electromagnetic modeling
  • Pre-/post-layout power system design and analysis
  • I/O buffer selection
  • Topology and termination definition
  • Clock system design/review
  • Pre-layout solution space analysis
  • Define decoupling strategy
  • Uncoupled and coupled analysis with power delivery
  • SSO
  • Crosstalk
  • ISI
  • Develop physical and electrical design rules (constraints) for the full system, including the PCBs, packages and IC, as required.
  • Post-layout verification
  • Power integrity analysis (see Power Integrity)

SME Design Review

In the design cycle, designers must contend with tight timelines, budgets, and technical challenges. Likewise, some portions of a design might be outsourced to an ODM partner in another country.

Acting as a second set of eyes, a Subject Matter Expert can review any design for good design practices and highlight any areas of concerns using a rating system. It is another tool that allows for the de-risking of the design.

Crosstalk

  • Determine limits during the pre-layout phase
  • Coupled interconnect models for solution space analysis capability
  • Composite effects of signal integrity, timing, and crosstalk are captured
  • Determine relative coupling metrics between signals.
  • Scanner inputs for each signal type based upon group type, edge-rates, and voltage swings.
  • Based on these results, specific nets or entire buses are simulated.
  • Extraction of critical signals is performed and simulations are run.

Timing Analysis

  • Detailed timing models created for each device.
  • Detailed evaluation of the system timing margins for the synchronous (common clock) and source synchronous buses within a design.
  • Eye diagrams are created
  • System timing is analyzed
  • Setup and hold margins are calculated
  • Trade offs between signal quality and timing examined