Layout Review

Sedona will review the physical layout against an engineering design release checklist. In addition, the revised layout will be checked against the list of known DFM concerns from Contract Manufacturers.

Specific checks can include, but are not limited to:
Pre-route Review Signoff

  • Physical implementation constraints and/or Design Intent Document review. Critical component placement; mechanical drawings and constraints, thermal constraints, related keep-in/keep-outs, termination placement constraints: Critical nets: diff pairs, power, clocks and high speed interfaces; termination requirements and placement.
  • Constraint validation and an overall sanity check.

Critical Placement Review

  • Check against Design Intent Document and mechanical drawings
  • Check programming and test header clearances, and orientation for easy access.
  • Check LEDS, switches and jumpers for visibility and access
  • Revisit problem areas and assess impact
  • Update and review current design intent if need be

Critical Route Signoff

  • Constraints classes for different signal classes defined.
  • All critical nets are named and constrained
  • All power pin escapes in heavy (12 mil) etch
  • All critical routing is checked – matched delays, diff pairs, stub lengths, symmetry, allowable via count
  • Test points identified and non-test pointed nets waived
  • Split plane breaks checked and no critical signal routed across any splits.
  • Power supply routing checked. Not potential moats/power starvation concerns
  • Power etches and planes have adequate stitching between layers
  • Board edge is stitched every .x” to chassis ground/static etch along all card edges

Completed Route Signoff

  • Reference Designators have been gridded per CM’s requirements
  • Reference Designators on backplane connectors agree with standardized assignment and should have not been changed with gridding operation
  • Power planes reviewed – thermal relief, antipads, split planes and signals crossing splits
  • Mounting holes have sufficient clearance to traces and planes
  • Sufficient grounding points - pads or stakes have been place around the board
  • Test points added and on appropriate grid. Match the testability requirements for the design
  • Non-constrained etch lengths have been compared and reviewed against Manhattan report
  • Parallelism report run – verify accumulation effects and layer-to-layer violations.
  • Check bus routing to ensure no unreasonable skew between bits.
  • Check critical nets were not unintentionally altered - glossed, rerouted during final routing and cleanup.
  • Check backplane/cable stub lengths, topology and loading
  • All critical nets FIXED are re-verified after ECO.
  • Make sure there are no thermals on press fit connectors
  • Valor has been run on board and all issues resolved or waived following review with engineering, fab. and/or CM.

Board Release Checklist

  • All DRC's have been checked and validated
  • Board successfully back annotated and an updated netlist validated by re-importing into Allegro.
  • Final BOM with back annotated reference designators generated – requires correct part number and revision number in schematic title block
  • Recheck that connector designators remained unchanged and are correct
  • Correct board number, revision, company name and serial number box markings exist and are appropriately sized and located
  • Re-generate final versions of PDF schematics

Fab Drawing Checks

  • Correct part number and revision
  • Stackup is correct and agrees with latest Fab stackup
  • Power/ground planes arrangement is in the correct sequence in stackup
  • Fab. notes include correct material, controlled impedance requirements and surface finish
  • Drill table has been updated and checked following any potential last minute changes
  • Verify Plated and non-plated holes agree with mechanical drawing
  • Standard hole tolerances on drills and dimensions are accurate +/- 3 mils
  • Tooling hole tolerances are +2/-0 mils

Assembly Drawing Checks

  • Verify drawing number and revision
  • Are mechanical items shown – heat sinks, screws, labels, clips etc. shown

Silkscreen Checks

  • No silkscreen over pads (Valor?)
  • All LEDS, jumpers, dip switches, test connectors labeled and visible
  • Ground test points labeled on bottom side
  • BGA’s pin escape vias have row/column marking bottom side for debug

Dependencies:

  • Copy of design schematics and PCB database
  • Timely delivery of revised schematics and revised PCB database