Schematic Review

Sedona will review each page of the schematic in conjunction with the BOM and current datasheets.

Typical checks will include, but are not limited to:

• Identification of any out of date information and potential impact to the design and functionality of any part rev. changes and errata.
• Specification review – checks for inconsistency between expected functionality and implementation.
• Correct connection checks, both power and signals – checking enhanced by custom scripts
• Correct and sufficient by-passing and filtering
• Consistent net naming conventions, diff-pairs, series terminated nets, buses etc.
• Correct use of hierarchical nets – global and local nets, unnamed and UNC’s ( no connects)
• Testability – ICT, JTAG chain integrity and test mode straps, unused output enables correctly strapped, test headers and loopback points and modes accessible and usable as designed.
• Initialization – race conditions, power sequencing, initial clock stability, hard and soft reset dependencies, mission mode and test modes straps.